This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-042729, filed Feb. 22, 1999, the entire contents of which are incorporated herein by reference.
This invention relates to a semiconductor device using a tensile-strained Si layer and a compressive-strained Sixe2x80x94Ge layer as the channel layers infield-effect transistors and a method of manufacturing the semiconductor device.
In ordinary semiconductor devices, a Si bulk has been used as a substrate and high-speed operation and less power consumption have been achieved by miniaturizing the constituting elements of the semiconductor devices. The miniaturization, however, is now coming closer to the physical and economical limitations. Thus, in the future, it will be necessary to establish the techniques for achieving high-speed operation and less power consumption by other approaches than the miniaturization.
For instance, the technique for achieving high-speed operation by using metal gates for gate electrodes to suppress delay in the wiring of gates has been developed. To form metal gates and high dielectric gate insulating films in CMOSFETs, a dummy gate process has been proposed (A. Chatterjee, et al., IEDM Tech. Dig., 1997, p. 821 and A. Chatterjee, et al., Japanese Patent Laid Open (kokai) No. 7-321222). The dummy gate process includes a process of forming a dummy gate, which is disposed in advance, in a region in which an actual gate is to be formed, then forming a source and a drain by self-alignment techniques with the dummy gate as a mask, and thereafter replacing the dummy gate with the actual gate.
The technique has difficulty of adjusting the threshold voltage of the transistor due to the influence of the work function of the metal gate. For instance, when a gate electrode is made of TiN, the value of the work function ranges from 4.3 to 4.6 eV. Thus, the gate electrode has the problem that the threshold voltage is higher than that of a conventional polysilicon electrode by about 0.4 to 0.5V.
To improve the carrier mobility in a channel layer, the technique for using a tensile-strained Si layer on an Sixe2x80x94Ge layer (under a tensile stress) as the channel layer of an N-MOS transistor and a compressive-strained Sixe2x80x94Ge layer (under a compressive stress) as the channel layer of a P-MOS transistor has been reported (K. Ismail, xe2x80x9cSi/Sixe2x80x94Ge High-Speed Field-Effect Transistors,xe2x80x9d IEDM Tech. Dig., 1995, p.509). By using a tensile-strained Si layer or a compressive-strained Sixe2x80x94Ge layer as the channel layers of MOS transistors, the mobility of electrons and holes at the surface increases, making high-speed operation compatible with less power consumption.
This technique, however, has the following problem: when a CMOSFET with a tensile-strained Si layer (n-channel layer) and a compressive-strained Sixe2x80x94Ge layer (p-channel layer) both formed as the channel layers is formed, the processes are complex and it is difficult to selectively form an NMOS channel layer and a PMOS channel layer. Since an Sixe2x80x94Ge layer is formed by a high-temperature heat treatment, the Sixe2x80x94Ge layer misfit dislocation or the segregation of Ge takes place, thereby degrading the gate breakdown voltage characteristic.
It is known that, when a MOSFET is operated on an SOI substrate, holes are accumulated in the substrate at the end of the channel layer (near the source) and what is called the floating body effect occurs, having an adverse effect on the operation of the device. To suppress the floating body effect, a method of making the source region of Sixe2x80x94Ge material to make the bandgap smaller than that of the channel layer (Si) and thereby drawing holes into the source region has been proposed (Akira Nishiyama, et al., xe2x80x9cFormation of Sixe2x80x94Ge source/drain using Ge implantation for floating-body effect resistant SOI MOSFETs,xe2x80x9d Jpn. J. Appl. Phys. Vol. 35, pp. 954-959, Part 1, No. 28, February 1996).
This method, however, has the problem of being unable to make the channel layer of Sixe2x80x94Ge material. That is, the method cannot make the improvement of the mobility of holes compatible with the suppression of the floating body effect.
As described above, an FET using a metal gate cannot secure sufficient driving current because of its higher threshold voltage.
Furthermore, it is difficult to form a CMOSFET in which an NMOSFET using a tensile-strained Si layer formed on an Sixe2x80x94Ge layer as a channel layer and a PMOSFET using a compressive-strained Sixe2x80x94Ge layer as a channel layer are used.
In addition, when the source region is made of Sixe2x80x94Ge material to make the bandgap smaller than that of the channel layer and thereby suppress the floating body effect of the FET formed at the surface of an SOI substrate, the Sixe2x80x94Ge material cannot be used for the channel layer, which prevents the device from operating faster.
An object of the present invention is to provide a semiconductor device capable of lowering the threshold voltage of a CMOSFET using a metal gate and improving the driving capability or the speed of the device and a method of manufacturing the semiconductor device.
Another object of the present invention is to provide a semiconductor device manufacturing method of easily forming a CMOSFET in which an NMOSFET using a tensile-strained Si. layer as a channel layer and a PMOSFET using a Sixe2x80x94Ge layer as a channel layer are used.
Still another object of the present invention is to provide a semiconductor device capable of making the improvement of the mobility of electrons in an FET formed at the surface of an SOI substrate compatible with the suppression of the floating body effect.
In a semiconductor device according to the present invention in which an NMOSFET and a PMOSFET have been formed in a silicon substrate, the gate electrodes of the NMOSFET and PMOSFET are made of metallic materials, an Sixe2x80x94Ge layer is formed in at least part of the surface regions including the respective channel layers of the NMOSFET and PMOSFET, and the concentration of Ge in the channel layer of the NMOSFET is lower than the concentration of Ge in the channel layer of the PMOSFET.
Preferred modes of the semiconductor device according to the present invention are as follows:
(a) The silicon substrate is an SOI substrate and the concentration of Ge in the channel layer of the MOSFET is lower than the concentration of Ge in the source of the MOSFET.,
(b) An Si layer on the Sixe2x80x94Ge layer is used as the channel layer of the NMOSFET and the Sixe2x80x94Ge layer is used as the channel layer of the PMOSFET. The thickness of the Si layer on the Sixe2x80x94Ge layer is ranged between 2 nm to 30 nm. The Sixe2x80x94Ge layer of the NMOSFET is formed as Si1xe2x88x92xGex(0.1xe2x89xa6xc3x97xe2x89xa60.9).
(c) A stacked structure of the Sixe2x80x94Ge layer and Si layer is formed only almost under the gate electrode of the channel region of the NMOSFET.
(d) The height of the surface of the gate electrode of the NMOSFET is equal to the height of the surface of the gate electrode of the PMOSFET.
(e) Gate insulating films for the NMOSFET and PMOSFET are made of Ta2O5.
(f) The part of the respective gate electrodes of the NMOSFET and PMOSFET are made of TiN.
(g) Gate insulating films for the NMOSFET and PMOSFET are made of Ta2O5 and the part of the respective gate electrodes of the NMOSFET and PMOSFET are made of TiN.
In a semiconductor device according to the present invention in which an NMOSFET is formed on a silicon substrate, the gate electrode of the NMOSFET is made of metallic material, and a tensile-strained Si layer on an Sixe2x80x94Ge layer is used as the channel layer of the NMOSFET.
Preferred modes of the semiconductor device are as follows:
(a) The silicon substrate is an SOI substrate and the concentration of Ge in the channel layer of the MOSFET is lower than the concentration of Ge in the source of the MOSFET.
(b) An Si layer on the Sixe2x80x94Ge layer is used as the channel layer of the NMOSFET and the Sixe2x80x94Ge layer is used as the channel layer of the PMOSFET.
(c) A stacked structure of the Sixe2x80x94Ge layer and Si layer is formed only almost under the gate electrode of the channel region of the NMOSFET.
A method of manufacturing semiconductor devices according to the present invention comprising: the step of forming a dummy gate in the gate formation region in each of an NMOSFET and a PMOSFET being formed in a silicon substrate; the step of selectively introducing impurities into the NMOSFET section and PMOSFET section at the surface of the silicon substrate with the dummy gates as masks and heating the impurity-introduced portions to form diffused layers serving as the sources and drains of the NMOSFET and PMOSFET; the step of forming an insulating film thicker than the dummy gates on the silicon substrate; the step of flattening the surface of the insulating film and exposing the top surface of the dummy gates; the step of removing the dummy gates and making a groove in the insulating film to allow the silicon substrate to be exposed at the bottom of the groove; the step of forming not only a stacked structure where an Si layer is formed on a first Sixe2x80x94Ge layer on the silicon substrate exposed in the groove on the NMOSFET region but also a second Sixe2x80x94Ge layer on the silicon substrate exposed in the groove on the PMOSFET region; the step of forming a gate insulating film on the exposed Si layer and Sixe2x80x94Ge layer; and the step of forming a gate electrode made of metallic material in the groove.
Preferred modes of the method for manufacturing the semiconductor device are as follows:
(a) The stacked structure of the first Sixe2x80x94Ge layer and Si layer on the NMOSFET side is formed by selectively introducing Ge into the silicon substrate exposed in the groove on the NMOSFET region and thereby forming the first Sixe2x80x94Ge layer in the region excluding the surface of the substrate, and the second Sixe2x80x94Ge layer on the PMOSFET side is formed by selectively introducing Ge into the surface of the silicon substrate exposed in the groove on the PMOSFET region.
(b) The step of forming a stacked structure of the first Sixe2x80x94Ge layer and Si layer on the NMOSFET side and a second Sixe2x80x94Ge layer on the PMOSFET side includes the step of selectively introducing Ge into the silicon substrate exposed in the groove on the NMOSFET region and PMOSFET region and thereby forming the first Sixe2x80x94Ge layer and second Sixe2x80x94Ge layer on the silicon substrate on the NMOSFET side and PMOSFET side, respectively, and the step of selectively growing an Si layer epitaxially at the surface of the first Sixe2x80x94Ge layer.
(c) The step of forming a stacked structure of the first Sixe2x80x94Ge layer and Si layer on the NMOSFET side and a second Sixe2x80x94Ge layer on the PMOSFET side includes the step of selectively growing epitaxially an Sixe2x80x94Ge layer on the silicon substrate exposed in the groove on the NMOSFET section side and PMOSFET side and thereby forming the first Sixe2x80x94Ge layer and second Sixe2x80x94Ge layer on the silicon substrate on the NMOSFET side and PMOSFET side, respectively, and the step of selectively growing an Si layer epitaxially on the surface of the first Sixe2x80x94Ge layer on the NMOSFET side.
A method of manufacturing semiconductor devices according to the present invention comprising: the step of forming a dummy gate in the gate formation region in each of an NMOSFET and a PMOSFET formed in a silicon substrate having an Sixe2x80x94Ge layer at its surface; the step of selectively introducing impurities into the PMOSFET section and NMOSFET section at the surface of the substrate with the dummy gates as masks and heating the impurity-introduced portions to form diffused layers serving as the sources and drains of the NMOSFET and PMOSFET; the step of forming an insulating film on the silicon substrate in such a manner that the film covers the dummy gates; the step of flattening the surface of the insulating film and exposing the top surface of the dummy gates; the step of removing the dummy gates and making a groove; the step of exposing the Sixe2x80x94Ge layer at the bottom of the groove on the NMOSFET section side; the step of selectively growing a silicon layer epitaxially on the Sixe2x80x94Ge layer exposed at the bottom of the groove on the NMOSFET section side; the step of exposing the Sixe2x80x94Ge layer at the bottom of the groove on the PMOSFET section side; the step of forming a gate insulating film on the Si layer on the NMOSFET section side and on the Sixe2x80x94Ge layer on the PMOSFET section side; and the step of forming a gate electrode made of metallic material in the groove.
With the above configuration, the present invention produces the following effects.
Since the gate electrode of the FET is made of metallic material, a part of the channel layer is formed as Sixe2x80x94Ge layer and the concentration of Ge in the channel layer of the NMOSFET is lower than that in the PMOSFET, the difference between the conduction band of the channel layer of the NMOSFET and the Fermi level of the gate electrode and the difference between the valence band of the channel layer of the PMOSFET and the Fermi level of the gate electrode are small. This helps prevent the threshold voltage from rising. In addition, a high-nobility, high-gate-breakdown-voltage metal (TiN) gate CMOS transistor can be realized using a simple manufacturing process including the dummy-gate process.
A low-threshold-voltage transistor using metal (TiN) gates for both an NMOS and a PMOS can be realized easily. The mobility of carriers is improved in both the NMOS and PMOS. The mobility of electrons is three to five times as high as and the mobility of holes is four to six times as high as that in an ordinary Si substrate.
Use of the metal gate prevents depletion from occurring in the gate and makes the effective thickness of the gate insulting film thinner. In addition, there is no delay in the wiring of the gate. Thus, a higher performance transistor can be formed. Moreover, since an NMOS gate and a PMOS gate need not be formed selectively, the number of manufacturing processes can be decreased.
Using the dummy gate process and Si or Sixe2x80x94Ge epitaxial growth techniques or Ge ion implantation techniques makes it easy to selectively form an NMOS channel layer (e.g., a tensile-strained Si layer) and a PMOS channel layer (e.g., an Sixe2x80x94Ge layer).
Use of the dummy gate process makes it possible to eliminate a heating process carried out at temperatures higher than 600xc2x0 C. after the formation of the Sixe2x80x94Ge channel layer. This suppresses the occurrence of misfit dislocation at the Sixe2x80x94Ge/Si interface or the segregation of Ge, which improves the gate breakdown voltage characteristic.
In the FET formed on the SOI substrate, by setting the Ge concentration at the under portion of the channel Si layer be lower than the Ge concentration of the source, the bandgap on the source side becomes smaller than the bandgap on the channel layer side and the holes accumulated in the Sixe2x80x94Ge layer (near the source) under the channel layer are drawn into the source. This suppresses the floating body effect.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.